This invention relates to a three-output level logic circuit provided with MOS transistors and more particularly to a type adapted for integration.
A three-output level logic circuit is a type which selectively sends forth a signal having a logic level "1" or "0" or a high impedance output signal. This three-output level logic circuit is indispensable as a drive circuit of a common bus of a central processing unit (CPU).
Description will now be given with reference to FIGS. 1 to 3 of the drawbacks of a conventional three-output level logic circuit. FIG. 1 includes an output stage and a drive stage. The output stage comprises an output terminal 1 for selectively producing a signal having a logic level "1" or "0" or high impedance output signal OUT, a first P type MOS transistor TR1 whose source drain path is connected between the output terminal 1 and a positive voltage source V.sub.DD, and a second N type MOS transistor TR2 whose source-drain path is connected between the output terminal 1 and a reference voltage source V.sub.SS (ground potential). The drive stage for activating the output stage comprises a first NAND circuit NAND1 which is supplied with a data signal D from a data signal supply terminal 2 and a control signal S from a control signal supply terminal 3 and delivers a gate signal IN1 to a gate electrode of the first MOS transistor TR1, and a second NAND circuit NAND2 which receives the data signal D through a first inverter NOT1 and also the control signal S and delivers the output signal thereof through a second inverter NOT2 to a gate electrode of the second MOS transistor TR2 as a gate signal IN2. TABLE 1 below indicates the relationship between the control signal S, data signal D, gate signal IN1, gate signal IN2 and output signal OUT as considered in terms of logic levels.
TABLE 1 ______________________________________ CONTROL DATA GATE GATE OUTPUT SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL S D IN1 IN2 OUT ______________________________________ 0 1 or 0 1 0 Hi-Z 1 0 1 1 0 1 0 0 1 ______________________________________
Hi-Z in TABLE 1 above denotes an output of high impedance state.
Referring to FIG. 1, inverters NOT1, NOT2 respectively have two MOS transistors. NAND circuits NAND1, NAND2 are respectively formed of four MOS transistors. Therefore, 14 MOS transistors have to be provided to constitute the logic circuit of FIG. 1. Therefore, the conventional logic circuit of FIG. 1 is accompanied with the drawbacks that the logic circuit occupies a large area; since a large number of gate stages for transmitting a signal are provided, it is difficult to operate the logic circuit at high speed; and involvement of 2-input logic circuits makes it complicated to lay out the logic circuit for integration.
Referring to FIG. 2 indicating another conventional three-output level logic circuit, the output stage has the same arrangement as that of FIG. 1. The drive stage of FIG. 2 comprises a first NOR circuit NOR1 which is supplied with a data signal D and control signal S, and delivers a gate signal IN1 to the gate electrode of the first MOS transistor TR1 through an inverter NOT4, and a second NOR circuit NOR2 which receives the data signal D through an inverter NOT3 and sends forth a gate signal IN2 to the gate electrode of the second MOS transistor TR2. The NOR circuits NOR1, NOR2 respectively have to be provided with four MOS transistors. Therefore, the logic circuit of FIG. 2 needs 14 MOS transistors as does that of FIG. 1, and consequently is accompanied with the same drawbacks as those which occur in FIG. 1. TABLE 2 below indicates the relationships between the data signal D, gate signals IN1, IN2 and output signal OUT as considered in terms of logic levels.
TABLE 2 ______________________________________ CONTROL DATA GATE GATE OUTPUT SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL S D IN1 IN2 OUT ______________________________________ 0 1 1 1 0 0 0 0 1 1 1 or 0 1 0 Hi-Z ______________________________________
The output stage of the conventional three-output level logic circuit of FIG. 3 comprises an MOS transistor TR3 of second conductivity type whose source-drain path is connected between the output terminal 1 and voltage source V.sub.DD, and an MOS transistor TR4 of second conductivity type whose source-drain path is connected between the output terminal 1 and reference voltage source V.sub.SS (ground potential). The drive stage of FIG. 3 comprises a NOR circuit NOR3 which receives a data signal D through an inverter NOT5 and also a control signal S and delivers a gate signal IN3 to the gate electrode of the MOS transistor TR3, and a NOR circuit NOR4 which receives the data signal D and control signal S and sends forth a gate signal IN4 to the gate electrode of the MOS transistor TR4. TABLE 3 below indicates the relationship between the control signal S, gate signals IN3, IN4 and output signal OUT of FIG. 3 as considered in terms of logic levels.
TABLE 3 ______________________________________ CONTROL DATA GATE GATE OUTPUT SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL S D IN3 IN4 OUT ______________________________________ 0 0 0 1 0 1 1 0 1 1 1 or 0 0 0 Hi-Z ______________________________________
The logic circuit of FIG. 3 can indeed be formed of 10 MOS transistors, but still is accompanied with the same problems described with respect to that of FIG. 1.